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Job requirements

1. Independently complete the verification task of ASIC function module, including: formulating verification scheme, building test environment, writing test ncentive, simulating and debugging;

2. Have the design of IP and chip level verification environment, including necessary modeling.

3. Be responsible for RTL / gate level simulation and code / function coverage analysis.

Master degree or above in computer science or related work experience.

5. Be familiar with common verification methods, languages and EDA, (UVM (Verilog / system Verilog, VCs / NC);

6. Relevant digital logic design / verification experience (FPGA or ASIC, including course projects);

7. Be familiar with C / C + + language, Perl, Python and other scripting languages;

8. Have processor design background such as arm and risc-v, and be familiar with SOC on-chip bus protocols such as AMBA and NOC is preferred;

9. Audio and video interface background such as Mipi, HDMI, DP, SPDIF and I2S is preferred;

10. USB, pcle, Ethernet, DDR, SD / EMMC, SPI, can and other interface background is preferred;

11. Knowledge background in artificial intelligence, video coding and decoding is preferred; Enterprising and teamwork spirit, good communication 

kills in Chinese and English

Job requirements1. Be responsible for module front-end design, including IP integration, module design and subsystem simulation;

2. Be responsible for chip level front-end design, including clock, reset, low power consumption, bus and overall chip set Become;

3. Use lint, CDC and other tools to complete RTL hand off;

4. Complete the design transplantation from ASIC to FPGA;

5. Cooperate with the back-end team to complete SDC quality inspection and netlist hand off;

6. Cooperate with the verification team to complete the verification work;

7. Cooperate with software personnel to complete the underlying driver development.

8. More than 3 years working experience in computer, electronics and other related majors

9. Be familiar with computer architecture and have experience in large-scale SoC design;

10. Be familiar with bus protocols, such as AMBA, ACE, Axi, APB;

11. Be familiar with common scripting languages (Perl, python, Makefile, etc.) and develop tools to improve design efficiency;

12. Have complete front-end design experience, master the use of common front-end EDA tools, and be familiar with lint, CDC and synthesis;

Job requirements1. Pay close attention to the cutting-edge technologies and products in the memory field, and put forward suggestions on the technical direction and product planning of the product line;

2. Participate in the design, development, function definition and chip architecture scheme discussion of the company's memory products;

3. Be responsible for designing customized solutions for Prom / EEPROM / flash / MTP / SRAM / DRAM;

4. Participate in the testing and debugging of the company's memory products and submit optimization plans;

5. Complete the preparation, maintenance and archiving of technical data and product documents;

6. Actively cooperate and implement other matters assigned by leaders;

7. Bachelor degree or above, major in microelectronics / semiconductor / integrated circuit / Electronics / communication / computer, etc

Job requirements

1. Full chip IO / ESD protection circuit network design, failure analysis and improvement of product ESD;

2. Development and verification of ESD circuit structure, including design and optimization of chip layout, pad location, special functions, DC characteristics, driving capability, noise tolerance capability, etc;

3. ESD / IO design and test;

4. Establish ESD IP database and technical indicators;

5. Bachelor degree or above in semiconductor device physics, microelectronics, electronic engineering and other related majors;

6.5 years of relevant working experience;

7. Master ESD / IO design and ESD / IO test methods;

8. Have the basis of analog circuit design, and skillfully use cadence software to IO design and simulate the circuit;

9. Be familiar with layout design of ESD circuit; Proactive working attitude, good team spirit

Job requirements

1. Complete DFT logic design, including: memory built-in self-test, memory built-in self repair, scan chain insertion, boundary scan chain insertion, macro test;

2. Complete DFT mode timing constraints to help DFT mode timing convergence;

3. Help the chip bring up, complete the debugging of test vector and improve the yield;

4. Master degree or higher in electronic engineering, unlimited working experience and rank;

5. Study hard and work actively;

6. Have the following single or multiple experiences: chip level testing, ASIC coding and simulation, design and implementation from RTL to GDS;

7. Enterprising and teamwork spirit, good communication skills,  fluent in Chinese and English.

Job requirements

1.Master degree or above in microelectronics, circuit and related;

2. More than 3 years of analog integrated circuit design experience;

3. Have a solid foundation of analog circuits, master the design process of analog integrated circuits, and have basic digital logic circuit design skills Statistical analysis ability;

4. Design flow with CMOS operational amplifier, AD / DA, bandgap, LDO, PLL or other analog circuits Film experience;

5. Master the use of analog integrated circuit design simulation software and layout design tools, and be familiar with the use of test and analysis tools;

Good English reading ability, good communication and execution ability, strong logical thinking and analysis ability.

Job requirements

1. Master degree, more than 5 years of experience in digital chip design and development;

2. Good digital circuit foundation, familiar with Verilog / VHDL;

3. be familiar with basic knowledge of digital signal processing;

4. Be familiar with image processing algorithm and TDC / ADC calibration algorithm;

5. Have practical experience in MCU system integration and verification, and be familiar with risc-v, 12C, SPI, JTAG and other common interfaces;

6. Proactive, good communication skills and teamwork skills;

7. Be familiar with script language and behavior model, such as TCL, Perl, Verilog, etc. and have relevant experience;

8. Be able to use cadence / Synopsys / mentor's main EDA tools.

Job requirements

1. Bachelor degree or above, major in integrated circuit, microelectronics, electronic engineering, communication, etc Industry;

2. More than 5 years experience in analog layout design;

3. Skillfully use special software tools in the industry;

4. Understand the mainstream process flow, and have the experience in the flow of 40nm and below process nodes;

5. Have general English reading and writing skills;

6. Proactive, strong communication skills, team spirit and able to work under pressure;

Experience in high-speed analog interface circuit design and layout design is preferred.

Job requirements:

1.Be responsible for the back-end process of digital circuit in the process of chip R & D and the implementation of digital analog mixed signal chip;

2. Complete the relevant processes of comprehensive synthesis conversion, formal verification, DFT and ATPG;

3. Proficient in flowplan, CTS, route, sta and physical verification (LVS / DRC...) Get GDS data

4. Connect eco and IR_ Drop and power analysis, and flow JDV inspection;

5. Bachelor degree or above, major in Microelectronics or chip, more than 5 years of relevant working experience, with strong script language (Perl / TCL / shell, etc.) programming ability;

6. Have good learning ability, communication and coordination ability and teamwork spirit.